RISC-V Toolchain and Compiler Optimization Techniques

RISC-V Toolchain and Compiler Optimization Techniques

As RISC-V has made it easier to bring up processor chipsets, the need for compiler engineers in the RISC-V ecosystem has increased. There is an implicit need for toolchain experts who can help RISC-V vendors gain an edge over competitors with their expertise in compilation technologies. Learning about internals of the toolchain, building and debugging RISC-V applications will allow you to work with thousands of companies that are building the latest hardware technologies.

This course is designed for engineers working with RISC-V vendors who are designing their own architectures, and those using RISC-V development boards to build applications. It is also useful for RISC-V application developers looking to improve performance or reduce the code size of their applications, toolchain developers, compiler engineers/performance engineers, and computer science students aspiring to major in systems software.

This course begins with an introduction to the compiler toolchain and concepts of cross-compilation. You will learn how to use popular compiler toolchains (both LLVM and GCC) to build RISC-V applications. You will also learn how to debug toolchain issues and what resources to consult when you need help. This course will help you optimize applications for code size or performance and gain an understanding of the demands of applications with instrumentation techniques.